An important step in the manufacture of integrated circuits is testing individual circuits to ensure that they are operational (i.e., that they produce correct outputs) and meet functional criteria such as temperature and speed requirements. In order properly test a circuit to find manufacturing errors, it is desirable to isolate sections of logic within the integrated circuit for testing.
A popular method of providing individual testing is referred to as "scan testing" in which a serial stream of data is propagated through the chip in a serial stream through a plurality of serially connected shift registers. After the registers are loaded, the data is output from some of these registers through the logic of the integrated circuit and the output of the logic is stored in other shift registers in the scan path. This data is then shifted out for observation.
One drawback of scan testing, particularly in latch-based designs, is that the shift registers are inefficiently used because data received from the stimulated logic overwrites data stored in the receiving shift registers. Hence, these receiving registers cannot be used to store test data to stimulate logic. Consequently, the scan path is unnecessarily long, which reduces the speed at which the testing apparatus may perform tests on the integrated circuit's logic.
Therefore, a need has arisen to provide a high-speed test architecture for testing the logic of an integrated circuit.